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MAX5078
4A, 20ns, MOSFET Driver
IN+
V IL
V IH
V DD
MAX5078A
MAX5078B
OUT
90%
IN-
BREAK-
P
t D-OFF1
t F
t D-ON1
10%
t R
IN+
BEFORE-
MAKE
CONTROL
N
OUT
IN-
V IH
V IL
t D-OFF2
RISING MISMATCH = t D-ON2 - t D-ON1
FALLING MISMATCH = t D-OFF2 - t D-OFF1
t D-ON2
GND
Figure 1. Timing Diagram
Use the following equation to calculate the series resistor:
Figure 2. MAX5054 Simplified Diagram (1 Driver)
The current required to charge and discharge the inter-
nal nodes is frequency dependent (see the I DD-SW
R GATE ≥
(L P + L S + L G )
C G
? R ON
Supply Current vs. Supply Voltage graph in the Typical
Operating Characteristics). The power dissipation (P Q )
due to the quiescent switching supply current (I DD-SW )
can be calculated as:
L P can be approximated as 2nH for the TDFN package.
L S is on the order of 20nH/in. Verify L G with the MOS-
FET vendor.
Supply Bypassing and Grounding
Pay extra attention to bypassing and grounding the
MAX5078A/MAX5078B. Peak supply and output currents
may exceed 4A when driving large external capacitive
loads. Supply voltage drops and ground shifts create
negative feedback for inverters and may degrade the
delay and transition times. Ground shifts due to poor
device grounding may also disturb other circuits sharing
the same AC ground return path. Any series inductance
in the V DD , OUT, and/or GND paths can cause oscilla-
tions due to the very high di/dt when switching the
MAX5078A/MAX5078B with any capacitive load. Place
one or more 0.1μF ceramic capacitors in parallel as close
to the device as possible to bypass V DD to GND. Use a
ground plane to minimize ground return resistance and
series inductance. Place the external MOSFET as close
as possible to the MAX5078A/MAX5078B to further mini-
mize board inductance and AC path impedance.
Power Dissipation
Power dissipation of the MAX5078A/MAX5078B consists
of three components: caused by the quiescent current,
capacitive charge/discharge of internal nodes, and the
output current (either capacitive or resistive load).
Maintain the sum of these components below the maxi-
mum power dissipation limit.
Maxim Integrated
P Q = V DD x I DD-SW
For capacitive loads, use the following equation to esti-
mate the power dissipation:
P CLOAD = C LOAD x (V DD ) 2 x f SW
where C LOAD is the capacitive load, V DD is the supply
voltage, and f SW is the switching frequency.
Calculate the total power dissipation (P T ) as follows:
P T = P Q + P CLOAD
Use the following equations to estimate the MAX5078A/
MA5078B total power dissipation when driving a ground-
referenced resistive load:
P T = P Q + P RLOAD
P RLOAD = D x R ON(MAX) x I LOAD 2
where D is the fraction of the period the MAX5078A/
MA5078B’s output pulls high, R ON(MAX) is the maximum
on-resistance of the device with the output high, and
I LOAD is the output load current of the MAX5078A/
MAX5078B.
Layout Information
The MAX5078A/MAX5078B MOSFET drivers source and
sink large currents to create very fast rising and falling
edges at the gate of the switching MOSFET. The high
di/dt can cause unacceptable ringing if the trace
lengths and impedances are not well controlled.
9
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